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00 12/16
6.2 Instruction Descriptions
6.2.1 Display Clear
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 1 01H
RS=0, /CS= 0, /WR= 0 to 1
This instruction
(1) Fills all locations in the display data RAM (DD-RAM) with 20H (Blank-character).
(2) Clear the contents of the address counter (ACC) to 00H.
(3) Sets the display for zero character shift (returns original position).
(4) Sets the address counter (ACC) to point to the DD-RAM.
(5) Sets the address counter (ACC) to increment on the each access of DD-RAM or CG-RAM.
6.2.2 Cursor Home
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 1 × 02H to 03H
× : Don’t care
RS=0, /CS= 0, /WR= 0 to 1
This instruction
(1) Clear the contents of the address counter (ACC) to 00H.
(2) Sets the address counter (ACC) to point to the DD-RAM.
(3) Sets the display for zero character shift (returns original position).
6.2.3 Entry Mode Set
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 1 I/D S 04H to 07H
RS=0, /CS= 0, /WR= 0 to 1
The I/D bit selects the way in which the contents of the address counter (ACC) are modified after
every access to DD-RAM or CG-RAM.
I/D = 1 : The address counter (ACC) is incremented.
I/D = 0 : The address counter (ACC )is decremented.
The S bit enables display shift, instead of cursor shift, after each write
or read to the DD-RAM.
S = 1 : Display shift enabled.
S = 0 : Cursor shift enabled.
The direction in which the display is shifted is opposite in sense to that of the cursor
.
For example, if S=0 and I/D=1,the cursor would shift on
e character to the right after a MPU writes to
DD-RAM. However if S=1 and I/D=1, the display would shift one character to the left and the cursor
would maintain its position on the panel.
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